The present invention relates to a voltage controlled oscillator for use in a phase locked loop for clock multiplication, for example in recovery of data pulses from a data stream input comprising digital data with unknown phase.
By embedding a clock signal into a transmitted data stream, a serial interface can operate at very high data rates without the timing skew problem between the clock and data signals. However, at the receiving end a clock/data recovery circuit is needed to recover the embedded clock signal from the incoming data stream and to retime the data.
Analog phase-locked loops (PLL) have traditionally been used for implementing the clock/data recovery circuit for high-speed applications. Although, in general, the analog PLL's can operate at very high frequencies, they tend to be more difficult to design than digital PLL's. For example, there is the problem of frequency drift, and analog PLL's are more sensitive to noise and to variations in processing and operation conditions.
However, there are also a few drawbacks associated with digital PLL's, for example the limitation on the operation speed and that they are generally worse than analog PLL's in terms of chip area and power consumption, and also when trying to reduce the number of pins of each chip package.